1. Field of the Invention
This application is directed to a circuit for preventing misoperation of an integrated circuit during the time period when an oscillator, which generates clock pulses used in the circuit reaches a stabilized state and more particularly, to an integrated circuit which includes an oscillator and a pair of gate circuits in the integrated circuit wherein one gate circuit triggers the oscillator to initiate operation thereof and the second gate circuit triggers an internal circuit in the integrated circuit after a period of time during which the oscillator is stabilized.
2. Description of the Prior Art
Low power consumption is always required in the C. MOS IC such as microprocessor LSI and therefore supply of clock to the internal logics is suspended using external standby control signal during non-operating condition by providing the standby mode. Simultaneously, it is also required to stop the operation of the oscillation circuit itself which generates the basic clock. However, use of a crystal resonator or ceramic resonator as the oscillation element requires at least several tens of milli-second (ms) until the oscillation output is stabilized after triggering the oscillation circuit. Therefore, when operation of the oscillator is initiated by means of an external control signal, there is an initial period during which the oscillator output is unstable. After this initial period, the oscillator output is stable in frequency and amplitude. The instability of the oscillator circuit output can result in misoperation of the processing unit and/or other internal circuits of the microprocessor IC. Thus, in order to prevent misoperation of the type described, it is necessary upon receipt of a control signal from an external source to initiate operation of the oscillator but to simultaneously prevent the application of the oscillator output to the internal logic circuits during the period of stabilization and after stabilization to apply the oscillator output, which is the clock signal, to the internal logic circuits.
One type of prior art misoperation prevention circuit for use with a C-MOS IC has a standby mode in which the internal logic circuits do not operate until after a predetermined period of time has elapsed from the initiation of oscillation. Prior art circuits of this type are shown in FIGS. 1 and 2.
Referring to FIG. 1, integrated circuit 1 includes an oscillator 3 which generates a clock signal which is applied to internal logic circuits which are part of the integrated circuit 1. The oscillation circuit 3 is triggered by a transistor 5 which as a control signal applied thereto, when a logic level of the control signal becomes high. The output of delay circuit 7 is applied to integrated circuit 1 to return the circuit to a operational mode after a predetermined period of time after the control signal is applied to the oscillator 3 via the transistor 5. The circuit of FIG. 1 has the disadvantage that it requires an external control circuit including the transistor 5, the delay circuit 7, and two control input terminals.
FIG. 2 illustrates another prior art type circuit, similar to FIG. 1, which eliminates the external circuits of FIG. 1 by incorporating the timer circuit 7' into the integrated circuit 1. The operation of the circuit in FIG. 2 is similar to that of FIG. 1. However, the circuit of FIG. 2 has the disadvantage that since the timer circuit 7' is part of the integrated circuit 1, the time period of the timer 7' cannot be adjusted. In addition, a large space is required for fabricating the timer circuit 7' in an IC chip, since several tens of transistors are necessary.